The present invention relates to a digital radio receiver, or in particular to an AGC (automatic gain control) method and an AGC circuit for controlling the level of the received signal.
The level of the signal received by the receiver used for digital radio communication changes with the propagation characteristics. An AGC circuit is required, therefore, for controlling the input signal of a demodulator at a constant level regardless of a change in the input signal level. Generally, an AGC circuit uses an amplifier, and the level of the received signal is regulated by changing the gain of the amplifier for amplifying the input signal. A method is widely known, in which a RSSI (received signal strength indicator) signal obtained by logarithmic amplification and envelope detection of the input received signal is used to control the gain of the amplifier.
An AGC method using an interval average of the RSSI signal will be explained with reference to FIG. 1.
FIG. 1 is a block diagram showing an example configuration of a conventional AGC circuit for performing the control operation using the interval average of the RSSI signal. In FIG. 1, reference numeral 101 designates an input terminal, numeral 102 an amplifier (for example, a variable gain amplifier), numeral 103 a RSSI circuit, numeral 104 an A/D (analog-to-digital) converter, numeral 105 an interval average calculation circuit, numeral 110 a gain control unit, numeral 111 a D/A (digital-to-analog) converter and numeral 112 a demodulation circuit.
In FIG. 1, the signal received by the digital radio receiver is applied through the input terminal 101 to the amplifier 102 and the RSSI circuit 103. The RSSI circuit 103 logarithmically amplifies the received signal applied thereto from the input terminal 101, and after envelope detection, outputs a RSSI signal. The RSSI output signal, as the result of logarithmic amplification and envelope detection, is proportional to the logarithm of the received signal level.
FIG. 2 is a block diagram showing in detail an example of the RSSI circuit 103. In FIG. 1, the received signal from the input terminal 101 is applied to an envelope detector 103a, and the output signal of the envelope detector 103a is applied to a logarithmic amplifier 103b, where it is logarithmically amplified. The signal thus logarithmically amplified is further applied to a low-pass filter (LPF) 103c for removing the amplitude variations caused by modulation, and outputted as a RSSI signal. The low-pass filter is intended to remove the amplitude variations due to the modulation and desirably has a time constant of not less than 2 symbols but not more than about 10 symbols. In the description of embodiments that follows, the time constant of the low-pass filter is assumed to be 2 symbols, for example.
FIG. 3 is a characteristic diagram showing the voltage of the RSSI output signal of the RSSI circuit versus the power of the received signal. The received signal power on the-abscissa is shown by logarithmic scale, and therefore the output voltage of the RSSI signal is proportional to the logarithm of the received signal power.
The RSSI output signal of the RSSI circuit 103 is converted into a digital signal in the A/D converter 104, and applied to the interval average calculation circuit 105. The RSSI signal, that has passed through the low-pass filter 103c having a time constant of 2 symbols, for example, is sampled by the A/D converter 104 for every 2 symbols. The RSSI signal sampled and converted into a digital signal in this way is hereinafter called an instantaneous value r of the RSSI signal. In the following explanation, the signal processing from the A/D converter 104 to the D/A converter 111 is performed by the digital signal processing, and the period of the operation clock signal (period of the operation clock timing) of this digital signal processing is two symbols. In the radio communication system, signal is generally transmitted and received on a frame unit basis of a predetermined data length. For example, when one frame is 40 msec and formed by 192 symbols, 2 symbols has a period of about 0.42 msec.
The interval average calculation circuit 105 calculates the input RSSI signal (the instantaneous value r of the RSSI signal) with a time constant (time tX) of a period longer than several tens of symbols, and applies the interval average value rX of the instantaneous values r of the RSSI signal providing the result of calculations to the gain control unit 110.
In the gain control unit 110, a control signal g for controlling the gain of the amplifier 102 is produced based on the input interval average value rX, and after being converted into an analog signal by the D/A converter 111, applied to the amplifier 102.
In the amplifier 102, the received signal input from the input terminal 101 is amplified with a gain corresponding to the control signal g input through the D/A converter 111, and the amplified signal is applied to the demodulation circuit 112.
The signal output from the amplifier 102 is a modulated wave, and this modulated wave signal is subjected to frequency change, detection and signal point determination in the demodulation circuit 112 thereby to retrieve the information contained in the modulated wave.
The signal received by the digital radio receiver is segmented for each frame, and the frame is roughly configured of a control information section containing the sync data and a data section. For example, FIG. 4 is a diagram for explaining the frame structure of a sync burst frame according to ARIB STD-T61 providing a standard specification of FDMA (frequency division multiple access). FIG. 5 is a diagram for explaining the frame structure of a traffic channel according to the same specification.
FIGS. 4 and 5, reference characters “LP+R” designates a linearizer preamble and ramp-up section, ad“Pb” a preamble section, “RI” a communication information channel section, “SW” a sync word pattern section, “PI” a parameter information channel section, “G” a guard time section, “Tch a traffic channel section, and “UD” an undefined section. The numeral values described under the respective symbols represent the number of bits for the areas thereof, respectively. The sections “LP+R” and “Pb” make up a control information section, and the remainders constitute a data section. The AGC operation is performed using a part of “LP+R” or “Pb”.
In the specification of FIG. 4, the modulation scheme is the π/4 shift QPSK (quaternary phase shift keying), a modulation rate of 4.8 kbaud, a frame length of 40 msec, and 192 symbols (384 bits; 1 symbol=2 bits) per frame.
FIG. 6 is a diagram showing an example of a transmission pattern. In FIG. 6, “SB0” and “SB1” are frames of the sync burst shown in FIG. 4, and “TchN” (N: natural number) a frame of the traffic channel shown in FIG. 5. In the example of FIG. 6, after two frames of sync burst are transmitted, N+1 frames of the traffic channel are transmitted. An explanation will be given below of the case in which the signal of the transmission pattern shown in FIG. 6 is received by the receiver.
FIGS. 7A to 7E are time charts showing the signal waveforms of the various parts for explaining the operation of the AGC circuit of FIG. 1. Specifically, these time charts represent the signal waveforms of the respective parts produced by the AGC operation performed with the interval average value rX of the RSSI signal using the AGC circuit shown in the block diagram of FIG. 1 in the case where the signals of frames n to n+k (n, k: integer) are applied to the receiver. FIG. 7A shows a received signal, FIG. 7B an instantaneous value r of the RSSI signal, FIG. 7C an interval average value rX of the RSSI signal, FIG. 7D a control signal g, and FIG. 7E an input signal to the demodulation circuit 112. In FIGS. 7A and 7E, the actual signal is a modulate wave and only the envelope is plotted by solid line while the modulated wave signal is not shown.
The AGC operation using the interval average value rX of the RSSI signal will be explained with reference to FIGS. 7A to 7E.
As shown in FIG. 7A, the received signal of frames n to n+k is input within the time of frames n−1 to n+k+1. In the frames n−1 and n+k+1 where the received signal is not input, therefore, the instantaneous value r of the RSSI signal assumes a minimum level, while the instantaneous value r of the RSSI signal assumes the level R shown in FIG. 7B in the frames n to n+k where the received signal is input.
The most simple frame structure is configured of preamble and data. The frame n is configured of a preamble and data as shown in FIG. 8A, and the frames n+1 to n+k may each be configured of data only as shown in FIG. 8B. A specific example of the preamble and the data is Nf=192 symbols and Np=44 symbols.
As shown in FIG. 7C, the interval average calculation circuit 105 determines the interval average value of the instantaneous values r (i.e. the average value of the instantaneous values r of the SSI signal during the time length tX) of the RSSI signal with a long time constant of not less than several tens of symbols, and therefore the interval average value rX takes a time for rise. The interval average is defined as an average value of the instantaneous values during a predetermined time length tX before the ith instantaneous value ri (i: arbitrary natural number) detected, and is determined at each detection time point (for every two symbols in the case under consideration) of the instantaneous value r.
Thus, as shown in FIG. 7D, the control signal g is gradually attenuated after assuming a maximum gain at the head of the frame n. As a result, as shown in FIG. 7E, the signal applied to the demodulation circuit 112 becomes an excessive input in the head portion of the frame n.